I/O port allocation

Many thanks to Mark Rison for providing the original information. Thankyou to Richard Wilson for his discoveries concerning RAM management I/O decoding.

This document will explain the decoding of the I/O ports. The port address is not decoded fully which means a hardware device can be accessed through more than one address, in addition, using some addressess can access more than one element of the hardware at the same time. The CPC IN/OUT design differs from the norm in that port numbers are defined using 16 bits, as opposed to the traditional 8 bits.

• IN r,(C)/OUT (C),r instructions: Bits b15-b8 come from the B register, bits b7-b0 come from "r"
• IN A,(n)/OUT (n),A instructions: Bits b15-b8 come from the A register, bits b7-b0 come from "n"

Listed below are the internal hardware devices and the bit fields to which they respond. In the table:

• "-" means this bit is ignored,
• "0" means the bit must be set to "0" for the hardware device to respond,
• "1" means the bit must be set to "1" for the hardware device to respond.
• "r1" and "r0" mean a bit used to define a register

Hardware device	Read/Write	Port bits
		b15	b14	b13	b12	b11	b10	b9	b8	b7	b6	b5	b4	b3	b2	b1	b0
Gate-Array	Write Only	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-
RAM Configuration	Write Only	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
CRTC	Read/Write	-	0	-	-	-	-	r1	r0	-	-	-	-	-	-	-	-